DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Preliminary 1
Version: DM9601-DS-P03 October 29, 2008
General Description
The DM9601 is a fully integrated and cost-effective single chip USB to Fast Ethernet MAC controller with 10/100 PHY. It is designed with the low power and high performance process. It is a 3.3V device with 5V tolerance then it supports 3.3V and 5V signaling.
The DM9601 provides USB transceiver compliant with USB1.1, 10/100M PHY, MAC controller, memory controller and an external MII interface to connect HPNA device or other support MII interface
transceiver. This chip already integrated 16K byte SRAM. The DM9601 interfaces to the UTP3, 4, 5 in
10Base-T and UTP5 in 100Base-TX. It is fully compliance with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9601 to take the maximum advantage of its abilities. The DM9601 is also support IEEE 802.3x full-duplex flow control.
The DM9601 supports 3 wake-up event to wake-up system from suspend mode. There are 7 GPIO pins (General purpose I/O) for user’s application.
Block Diagram
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
2 Preliminary
Version: DM9601-DS-P03 October 29, 2008
Features
■ USB Characteristics: z USB Specification revision 1.1 compliant z Supports 12Mb/s Full-Speed operation z Supports suspend mode and remote wake-up resume
z Supports USB standard commands z Supports vendor specific commands z Supports test-mode for memory test. z
Efficient TX/RX FIFO auto management.
■ Transceiver: z 10/100M PHY z USB 1.1
■ Others:
z Supports large internal 16K byte SRAM z Supports automatically load vendor ID and product ID from EEPROM
z Supports MII and reverse MII interface z IEEE802.3x flow control for full-duplex mode z Back Pressure Mode for half-duplex mode flow control
z
Supports wakeup frame, link status change and Magic packet events for remote wake-up z Low-Power, Single-Supply 3.3V CMOS
technology z
Very Low Power Consumption mode ¾ Power Reduced mode(cable detection) ¾ Power Down mode
¾ Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. z
Compatible with 3.3V and 5.0V tolerant I/O z 100-pin LQFP
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Preliminary 3
Version: DM9601-DS-P03 October 29, 2008
Pin Configuration: 100 Pin LQFP & with MII Interface Mode
T X D 1
BGRES
AGND NC LINK_O WAKEUP PW_RST#
DGND NC N C GPIO4GPIO5GPIO6
NC NC NC NC NC DVDD NC NC NC NC NC NC NC DGND
NC
N C N C N C D V D D N C N C N C N C N C N C N C N C N C D G N D T E S T 1T E S T 2T E S T 3T E S T 4D V D D X 2_25M X 1_25M D G N D S D A G N D
AVDD AVDD RX+RX-AGND AGND TXO+TXO-AVDD DVDD LINK_I RXD0RXD1RXD2RXD3DGND CRS COL RX_DV RX_ER RX_CLK TEST5TX_CLK TXD0T X D 2T X D 3T X _E N D V D D M D I O M D C D G N D C L K 20M O S P E E D #D U P #L I N K A C T #D G N D E E D I E E D O E E C K E E C S G P I O 0G P I O 1G P I O 2G P I O 3D V D D A V D D D M D P
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
4 Preliminary
Version: DM9601-DS-P03 October 29, 2008
Pin Description
Pin No. Pin Name
Type
Description
MII Interface
37 LINK_I I/O External MII device link status. 38,39,40,
41 RXD[3:0] I/O External MII Receive Data
43 CRS I/O External MII Carrier Sense
44 COL I/O External MII Collision Detect 45
RX_DV
I/O
External MII Receive Data Valid
46 RX_ER I/O External MII Receive Error 47 RX_CLK I/O External MII Receive Clock 49 TX_CLK I/O External MII Transmit Clock 50,51,52,
53 TXD[3:0]
I/O External MII Transmit Data 54 TX_EN
I/O External MII Transmit Enable 56 MDIO I/O MII Serial Management Data 57
MDC
I/O
MII Serial Management Data Clock
EEPROM Interface
64 EEDI I/O Data from EEPROM 65 EEDO I/O Data to EEPROM
66
EECK
I/O
Clock to EEPROM
67 EECS O
Chip Select to EEPROM
This pin is used as a strap pin to define the LED modes. When it is pull-high, the LED mode is the mode 1; Otherwise it is mode 0.
USB Interface
74 DM I/O USB Data Minus 75
DP
I/O USB Data Plus Clock Interface
21 X2_25M I/O Crystal 25MHz Out 22 X1_25M I/O Crystal 25MHz In 59
CLK20MO
I/O 20Mhz clock output LED Interface
60 SPEED100# O Speed LED It is low output to indicate that the internal PHY is operated in 100M
speed, or it is floating for the 10M mode of the internal PHY. 61 DUP#
O
Full-duplex LED In LED mode 1, It is low output to indicate that the internal PHY is
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Preliminary 5
Version: DM9601-DS-P03 October 29, 2008
operated in full-duplex mode, or it is floating for the half-duplex mode of the internal PHY.
In LED mode 0, It is low output to indicate that the internal PHY is
operated in 10M mode, or it is floating for the 100M mode of the internal PHY.
62 LINK&ACT#
O Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of the internal PHY.
In LED mode 0, it is the LED of the carrier sense signal of the internal PHY only. 10/100 PHY/Fiber
24 SD I Fiber-optic signal detect PECL signal which indicates whether or not the fiber-optic receives pair
is receiving valid levels. 25 AGND Bandgap ground. 26 BGRES I/O Bandgap pin. 27 AVDD Bandgap and guard ring power 28 AVDD
RX power
29 RX+ I TP RX input 30
RX-
I
TP RX input 31 AGND RX ground 32 AGND TX ground 33 TXO+ O TP TX output 34
TXO-
O
TP TX output
35 AVDD TX power
Miscellaneous
16,17,18
19
TEST1~TEST4 I
Operation Mode, tie to ground in application. Tie TEST1 to high if external PHY is used. 48 TEST5 I It must be ground.
68,69,70, 71,82,83, 84 GPIO0~6 I/O General I/O ports
Registers GPCR and GPR can program these pins. The GPIO0 is output mode with output data high at default to power
down internal PHY and other external MII device.
GPIO1~6 default are input ports. 78 LINK_O O Cable link status output. Active High.
This pin is also used as a strap pin to define the MII interface is
reversed MII interface (pull-high) or normal MII interface (not pull-high).
79 WAKEUP O Issue a wake-up signal when wake-up event happens.
80 PW_RST# I
Hardware Reset
Active low signal to initiate the DM9601.
1,2,3,4,6,7,8,9,10,11,
12,13,14, 77,85,86, 87,88,89,
NC Not Connect
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
6 Preliminary
Version: DM9601-DS-P03 October 29, 2008
91,92,93, 94,95,96, 97,98,100 Power
5,20,36,55,
72,90, DVDD Digital VCC
通信工程考研15,23,42,
58,63, 81,99
DGND Digital GND 73 AVDD Analog VCC
76 AGND Analog GND
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