专利名称：DETRIMENTAL LATCH-UP AVOIDANS IN DIGITAL CIRCUITS
发明人：PLESNER, ERIK,HANSEN, MORTEN, SKOV 申请号：SE0101556
申请日：20010705
公开号：WO0200004A3
公开日：
sidselrasmussen
20020516
专利内容由知识产权出版社提供
摘要：The present invention relates to methods and arrangement to prevent detrimental latch-up in gates located in two independently powered supply domains. The gates are mutually connected via a bi-directional interface between the domains, and a voltage surveillance circuit is associated with the domains. The method comprises the following steps: detecting in the surveillance circuit, an improper supply of power to at least one domain of the two domains; generating an inhibit signal in the surveillance circuit; preventing logic high levels for signals on the bi-directional interface between gates located in the two domains.
申请人：TELEFONAKTIEBOLAGET LM ERICSSON (PUBL),PLESNER, ERIK,HANSEN, MORTEN, SKOV
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