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All other trademarks and registered trademarks are the property of their respective owners.All specifications are subject to change without notice.
Features
•Lowest power 32macrocell CPLD •  5.0ns pin-to-pin logic delays •System frequencies up to 200MHz •32macrocells with 750usable gates •
Available in small footprint packages -48-ball CS BGA (36user I/O pins)-44-pin VQFP (36user I/O)-44-pin PLCC (36user I/O)
•
Optimized for 3.3V systems -Ultra-low power operation
-5V tolerant I/O pins with 3.3V core supply
-Advanced 0.35micron five layer metal EEPROM
process
-Fast Zero Power™(FZP)CMOS design
technology •
Advanced system features -In-system programming -Input registers
-Predictable timing model
-Up to 23available clocks per function block -Excellent pin retention during design changes -Full IEEE Standard 1149.1boundary-scan (JTAG)-Four global clocks
-Eight product term control terms per function block •Fast ISP programming times
•Port Enable pin for dual function of JTAG ISP pins •  2.7V to 3.6V supply voltage at industrial temperature range
•Programmable slew rate control per macrocell •Security bit prevents unauthorized access •
Refer to XPLA3family data sheet (DS012)for architecture description
Description
The XCR3032XL is a 3.3V,32-macrocell CPLD targeted at power sensitive designs that require leading edge program-mable logic solutions.A total of two function blocks provide 750usable gates.Pin-to-pin propagation delays are 5.0ns with a maximum system frequency of 200MHz.
TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD,both in process technol-ogy and design technique.Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach.This CMOS gate imple-mentation allows Xilinx to offer CPLDs that are both high performance and low power,breaking the paradigm that to have low power,you must have low performance.Refer to Figure 1and Table 1showing the I CC vs.Frequency of our XCR3032XL TotalCMOS CPLD (data taken with two resetable up/down,16-bit counters at 3.3V,25°C).
XCR3032XL 32Macrocell CPLD
DS023(v1.6)June 27,2002Preliminary Product
Specification
Figure 1:I CC vs.Frequency at V CC =3.3V,25°C
5
010
15
20
20
zia40
60
80
100
120
140
160
180
200
Frequency (MHz)
DS023_01_080101
T y p i c a l  I C C (m A )
Table 1:I CC vs.Frequency (V CC =3.3V,25°C)
Frequency (MHz)015102050100200Typical I CC (mA)
0.02
0.13
0.54
1.06
2.09
5.2
10.26
20.3
元器件交易网b2b
2
DS023(v1.6)June 27,2002
1.See XPLA3family data sheet (DS012)for recommended operating conditions
2.See Figure 2for output drive characteristics of the XPLA3family.
3.This parameter guaranteed by design and characterization,not by testing.
4.Typical leakage current is less than 1µA.
5.See Table 1,Figure 1for typical values.
6.This parameter measured with a 16-bit,resetable up/down counter loaded into every function block,with all outputs disabled and
unloaded.Inputs are tied to V CC or ground.This parameter guaranteed by design and characterization,not testing.7.Typical values,not tested.
Figure 2:Typical I/V Curve for the XPLA3Family,3.3V,25°C
0102030405060
7080901000.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Volts
I OL (3.3V)
I OH (3.3V)
I OH (2.7V)
m A
DS012_10_031802
Symbol Parameter
-
5-7-10
Unit Min.Max.Min.Max.Min.Max.
T PD1Propagation delay time(single p-term)  4.5-7.0-9.1ns T PD2Propagation delay time(OR array)(3)  5.0-7.5-10.0ns T CO Clock to output(global synchronous pin clock)  3.5  5.0-  6.5ns T SUF Setup time(fast input register)  2.5-  3.0-  3.0-ns T SU1(4)Setup time(single p-term)  3.0-  4.3-  5.4-ns T SU2Setup time(OR array)  3.5-  4.8-  6.3-ns T H(4)Hold time0-0-0-ns T WLH(4)Global Clock pulse width(High or Low)  2.5-  3.0-  4.0-ns T PLH(4)P-term clock pulse width  4.0-  5.0-  6.0-ns T R(4)Input rise time-20-20-20ns T L(4)Input fall time-20-20-20ns f SYSTEM(4)Maximum system frequency-200-119-95MHz T CONFIG(4)Configuration time(5)-30-30-30µs T INIT(4)ISP initialization time-30-30-30µs T POE(4)P-term OE to output enabled-7.2-9.3-11.2ns T POD(4)P-term OE to output disabled(6)-7.2-9.3-11.2ns T PCO(4)P-term clock to output-  6.0-8.3-10.7ns T PAO(4)P-term set/reset to output valid-  6.5-9.3-11.2ns Notes:
1.Specifications measured with one output switching.
2.See XPLA3family data sheet(DS012)for recommended operating conditions.
3.See Figure4for derating.
4.These parameters guaranteed by design and/or characterization,not testing.
5.Typical current draw during configuration is3mA at3.6V.
6.Output C L=5pF.
4
DS023(v1.6)June 27,2002
Internal Timing Parameters (1,2)
Symbol Parameter
-5
-7-10
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Buffer Delays T IN Input buffer delay -0.7-  1.6-  2.2ns T FIN Fast Input buffer delay -  2.2-  3.0-  3.1ns T GCK Global Clock buffer delay -0.7-  1.0-  1.3ns T OUT Output buffer delay
-  1.8-  2.7-  3.6ns T EN Output buffer enable/disable delay
-  4.5
-  5.0
-  5.7
ns
Internal Register,Product Term,and Combinatorial Delays
T LDI Latch transparent delay -  1.3-  1.6-  2.0ns T SUI Register setup time    1.0-  1.0-  1.2-ns T HI Register hold time
0.3-0.5-0.7-ns T ECSU Register clock enable setup time    2.0-  2.5-  3.0-ns T ECHO Register clock enable hold time    3.0-  4.5-  5.5-ns T COI Register clock to output delay -  1.0-  1.3-  1.6ns T AOI Register async.S/R to output delay -  2.0-  2.3-  2.1ns T RAI very -  3.5-  5.0-  6.0ns T PTCK Product term clock delay
-  2.5-  2.7-  3.3ns T LOGI1Internal logic delay (single p-term)-  2.0-  2.7-  3.3ns T LOGI2Internal logic delay (PLA OR term)
-  2.5
-  3.2
-  4.2
ns
Feedback Delays
T F ZIA delay
-0.5
-  2.9
-  3.5
ns
Time Adders
T LOGI3Fold-back NAND delay -  2.0-  2.5-  3.0ns T UDA Universal delay -  1.2-  2.0-  2.5ns T SLEW
Slew rate limited delay
-  4.0
-
  5.0
-  6.0
ns
Notes:
1.These parameters guaranteed by design and characterization,not testing.
2.See XPLA3family data sheet (DS012)for timing model.
Switching Characteristics
Figure 3:AC Load Circuit
Figure 4:Derating Curve for T PD2
3.0
3.5
4.0
4.5
124816
DS023_05_061101
Outputs
T P D (n s
)
Figure 5:Voltage Waveform
6
DS023(v1.6)June 27,2002
Pin Descriptions
Table 2:XCR3032XL User I/O Pins
Notes:
1.Port Enable is brought High to enable JTAG pins when
JTAG pins are used as I/O.See family data sheet (DS012)for full explanation.
Table 3:XCR3032XL I/O Pins