TMS320C6745,TMS320C6747Fixed-and Floating-Point Digital Signal Processor 1TMS320C6745,TMS320C6747Fixed-and Floating-Point Digital Signal Processor 1.1Features
•Software Support
–TI DSP/BIOS™
–Chip Support Library and DSP Library
•375-and456-MHz TMS320C674x VLIW DSP
•C674x Instruction Set Features
–Superset of the C67x+and C64x+ISAs
–Up to3648MIPS and2736MFLOPS C674x
–Byte-Addressable(8-,16-,32-,and64-Bit Data)–8-Bit Overflow Protection
–Bit-Field Extract,Set,Clear
–Normalization,Saturation,Bit-Counting
–Compact16-Bit Instructions
•C674x Two-Level Cache Memory Architecture –32KB of L1P Program RAM/Cache
–32KB of L1D Data RAM/Cache
–256KB of L2Unified Mapped RAM/Cache
–Flexible RAM/Cache Partition(L1and L2)•Enhanced Direct Memory Access Controller3 (EDMA3):
–2Transfer Controllers
–32Independent DMA Channels
–8Quick DMA Channels
–Programmable Transfer Burst Size
•TMS320C674x Fixed-and Floating-Point VLIW DSP Core
–Load-Store Architecture with Nonaligned Support
–64General-Purpose Registers(32-Bit)
–Six ALU(32-and40-Bit)Functional Units –Supports32-Bit Integer,SP(IEEE Single Precision/32-Bit)and DP(IEEE Double
Precision/64-Bit)Floating Point
–Supports up to Four SP Additions Per Clock, Four DP Additions Every2Clocks
–Supports up to Two Floating-Point(SP or DP) Reciprocal Approximation(RCPxP)and
Square-Root Reciprocal Approximation
(RSQRxP)Operations Per Cycle
–Two Multiply Functional Units
–Mixed-Precision IEEE Floating Point Multiply Supported up to:
–2SP x SP->SP Per Clock
–2SP x SP->DP Every Two Clocks
–2SP x DP->DP Every Three Clocks
–2DP x DP->DP Every Four Clocks –Fixed-Point Multiply Supports Two32x32-Bit
Multiplies,Four16x16-Bit Multiplies,or
Eight8x8-Bit Multiplies per Clock Cycle,and
Complex Multiples
–Instruction Packing Reduces Code Size
–All Instructions Conditional
–Hardware Support for Modulo Loop
Operation
–Protected Mode Operation
–Exceptions Support for Error Detection and Program Redirection
•128KB of RAM Shared Memory(TMS320C6747 Only)
•  3.3-V LVCMOS I/Os(Except for USB Interfaces)•Two External Memory Interfaces:
–EMIFA
–NOR(8-or16-Bit-Wide Data)
–NAND(8-or16-Bit-Wide Data)
–16-Bit SDRAM with128-MB Address Space (TMS320C6747Only)
–EMIFB
–32-Bit or16-Bit SDRAM with256-MB
Address Space(TMS320C6747)
–16-Bit SDRAM with128-MB Address Space (TMS320C6745)b总001
•Three Configurable16550-Type UART Modules:–UART0with Modem Control Signals
–Autoflow Control Signals(CTS,RTS)on UART0 Only
–16-Byte FIFO
–16x or13x Oversampling Option
•LCD Controller(TMS320C6747Only)
•Two Serial Peripheral Interfaces(SPIs)Each with One Chip Select
•Multimedia Card(MMC)/Secure Digital(SD)Card Interface with Secure Data I/O(SDIO)
•Two Master and Slave Inter-Integrated Circuit(I2C Bus™)
•One Host-Port Interface(HPI)with16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
(TMS320C6747Only)
•Programmable Real-Time Unit Subsystem (PRUSS)
–Two Independent Programmable Realtime Unit (PRU)Cores
–32-Bit Load and Store RISC Architecture
–4KB of Instruction RAM per Core
–512Bytes of Data RAM per Core
2TMS320C6745,TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Submit Documentation Feedback Product Folder Links:TMS320C6745TMS320C6747
TMS320C6745,TMS320C6747Fixed-and Floating-Point Digital Signal Processor Copyright ©2008–2014,Texas Instruments Incorporated
–PRUSS can be Disabled via Software to Save Power –Standard Power-Management Mechanism –Clock Gating –Entire Subsystem Under a Single PSC Clock Gating Domain –Dedicated Interrupt Controller –Dedicated Switched Central Resource •
USB 1.1OHCI (Host)with Integrated PHY (USB1)(TMS320C6747Only)•
USB 2.0OTG Port with Integrated PHY (USB0)–USB 2.0High-and Full-Speed Client (TMS320C6747)–USB 2.0Full-Speed Client (TMS320C6745)–USB 2.0High-,Full-,and Low-Speed Host (TMS320C6747)–USB 2.0Full-and Low-Speed Host (TMS320C6745)–High-Speed Functionality Available on TMS320C6747Device Only –End Point 0(Control)–End Points 1,2,3,4(Control,Bulk,Interrupt or ISOC)RX and TX •
Three Multichannel Audio Serial Ports (McASPs):–TMS320C6747Supports 3McASPs –TMS320C6745Supports 2McASPs –Six Clock Zones and 28Serial Data Pins –Supports TDM,I2S,and Similar Formats –DIT-Capable (McASP2)–FIFO Buffers for Transmit and Receive •10/100Mbps Ethernet MAC (EMAC):
–IEEE 802.3Compliant (3.3-V I/O Only)–RMII Media-Independent Interface –Management Data I/O (MDIO)Module •Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747Only)•One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)•One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)•Three Enhanced Pulse Width Modulators (eHRPWMs):–Dedicated 16-Bit Time-Base Counter with Period and Frequency Control –6Single Edge,6Dual Edge Symmetric,or 3Dual Edge Asymmetric Outputs –Dead-Band Generation –PWM Chopping by High-Frequency Carrier –Trip Zone Input •Three 32-Bit Enhanced Capture (eCAP)Modules:–Configurable as 3Capture Inputs or 3Auxiliary Pulse Width Modulator (APWM)Outputs –Single-Shot Capture of up to Four Event Time-Stamps •Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP)Modules •TMS320C6747Device:–256-Ball Pb-Free Plastic Ball Grid Array (PBGA)[ZKB Suffix],1.0-mm Ball Pitch •TMS320C6745Device:–176-pin PowerPAD™Plastic Quad Flat Pack [PTP suffix],0.5-mm Pin Pitch •Commercial,Industrial,Extended,or Automotive
Temperature
1.2Applications •A/V Receivers •Automotive Amplifiers •Soundbars
•Home Theatre Systems
•Professional Audio
•Network Streaming Audio 1.3Description
The TMS320C6745/6747device is a low-power digital signal processor based on a TMS320C674x DSP core.It consumes significantly lower power than other members of the TMS320C6000™platform of DSPs.
The TMS320C6745/6747device enables original-equipment manufacturers (OEMs)and original-design manufacturers (ODMs)to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747DSP core uses a two-level cache-based architecture.The Level 1program cache (L1P)is a 32-KB direct mapped cache and the Level 1data cache (L1D)is a 32-KB 2-way set-a
ssociative cache.The Level 2program cache (L2P)consists of a 256-KB memory space that is shared between program and data space.L2memory can be configured as mapped memory,cache,or combinations of the two.Although the DSP L2is accessible by other hosts in the system,an additional 128KB of RAM shared memory (TMS320C6747only)is available for use by other hosts without affecting DSP performance.