October 2011Doc ID 022108 Rev 11/22
AN3969
Application note
EEPROM emulation in STM32F40x/STM32F41x microcontrollers
Introduction
EEPROMs (Electrically Erasable Programmable Read-Only Memory) are often used in industrial applications to store updateable data. An EEPROM is a type of permanent (non-volatile) memory storage system used in complex systems (such as computers) and other electronic devices to store and retain small amounts of data in the event of power failure.For low-cost purposes, external EEPROM can be replaced using one of the following features of STM32F40x/STM32F41x:
●
On-chip 4 Kbytes backup SRAM ●On-chip Flash, with specific software algorithm
The STM32F40x/STM32F41x features 4 Kbytes backup SRAM that can be powered from the VBAT supply when the main VDD supply is powered off.
This backup SRAM can be used as internal EEPROM (without any additional software) as long as the VBAT is present (typically in battery powered application) with the advantage of high speed access at CPU frequency.
However, when the backup SRAM is used for other purposes and/or the application does not use the VBAT supply, the on-chip Flash memory (with a specific software algorithm) can be used to emulate EEPROM memory.
This application note describes the software solution for substituting standalone EEPROM by emulating the EEPROM mechanism using the on-chip Flash of STM32F40x/STM32F41x devices.
Emulation is achieved by employing at least two sectors in the Flash. The EEPROM emulation code swaps data between the sectors as they become filled, in a manner that is transparent to the user.
The EEPROM emulation driver supplied with this application note meets the following requirements:
●
Lightweight implementations offering a simple API that consists of three functions for initialization, read data and write data, and reduced footprint.●
Simple and easily updateable code model ●
Clean-up and internal data management transparent to the user ●
Background sector erase ●At least two Flash memory sectors to be used, more if possible for wear leveling The EEPROM size to be emulated is flexible, within the limits and constraints of the sector size, and allows for a maximum EEPROM size.
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Contents AN3969
Contents
1Main differences between external and emulated EEPROM . . . . . . . . . 5
1.1Difference in write access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2Difference in erase time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3Similarity in writing method  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2Implementing EEPROM emulation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2Case of use: application example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3EEPROM emulation software description  . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4EEPROM emulation memory footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5EEPROM emulation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3Embedded application aspects  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1Data granularity management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2Wear leveling: Flash memory endurance improvement . . . . . . . . . . . . . . 16
3.2.1Wear-leveling implementation example . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3Page header recovery in case of power loss  . . . . . . . . . . . . . . . . . . . . . . 17
3.4Cycling capability and page allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1Cycling capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.2Flash page allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5Real-time consideration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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AN3969List of tables List of tables
Table 1.Differences between external and emulated EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2.Emulated pages possible status and corresponding actions . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. STM32F40x/STM32F41x Flash memory sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ta
ble 4.API definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5.Memory footprint for EEPROM emulation mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6.EEPROM emulation timings with a 168 MHz system clock . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7.Flash program functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8.Application design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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List of figures AN3969 List of figures
Figure 1.Header status switching between page0 and page1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2.EEPROM variable format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3.Data update flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4.WriteVariable flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5.Flash memory footprint for EEPROM emulation (mechanism and storage). . . . . . . . . . . . 14 Figure 6.Page swap scheme with four pages (wear leveling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4/22Doc ID 022108 Rev 1
1 Main differences between external and emulated
EEPROM
EEPROM is a key component of many embedded applications that require non-volatile
storage of data updated with byte or word granularity during run time.
Microcontrollers used in these systems are more often based on embedded Flash memory.
To eliminate components, save PCB space and reduce system cost, the
STM32F40x/STM32F41x Flash memory may be used instead of external EEPROM for
simultaneous code and data storage.
Unlike Flash memory, however, external EEPROM does not require an erase operation to
free up space before data can be rewritten. Special software management is required to
store data in embedded Flash memory.
The emulation software scheme depends on many factors, including the EEPROM reliability,
the architecture of the Flash memory used, and the product requirements.
The main differences between embedded Flash memory and external serial EEPROM are
the same for any microcontroller that uses the same Flash memory technology (it is not
specific to the STM32F40x/STM32F41x family products). The major differences are
summarized in Table1.
Table 1.Differences between external and emulated EEPROM
Feature
External EEPROM
(for example, M24C64:
I²C serial access EEPROM)
Emulated EEPROM using on-
chip Flash memory
Emulated EEPROM using on-
chip backup SRAM memory (1)
Write time –Random byte Write within 5
ms. Word program time = 20
ms
–Page (32 bytes) Write within
5 ms. Word program time =
625 µs
Half-word program time: from 30
µs to 237.25 ms (2)
CPU speed with 0 wait state
Erase time N/A Sector (large page) Erase time: from 1s to 3 s (depending on the sector size)
NA
Write method –Once started, is not CPU-
dependent
–Only needs proper supply
Once started, is CPU-
dependent.
If a Write operation is interrupted
by CPU reset, the EEPROM
Emulation algorithm is stopped,
but current Flash write operation
is not interrupted by a software
reset.
Can be accessed as bytes (8
bits), half words (16 bits) or full
words (32 bits).
Can be accessed as bytes (8
bits), half words (16 bits) or full
words (32 bits).
Write operation is interrupted by
a software reset.
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6/22Doc ID 022108 Rev 11.1 Difference in write access time
Because Flash memories have a shorter write access time, critical parameters can be stored faster in the emulated EEPROM than in an external serial EEPROM, thereby
improving data storage.
1.2 Difference in erase time
The difference in erase time is the other major difference between a standalone EEPROM and emulated EEPROM using embedded Flash memory. Unlike Flash memories,
EEPROMs do not require an erase operation to free up space before writing to them. This means that some form of software management is required to store data in Flash memory. Moreover, as the erase process of a block in the Flash memory does not take long, power shutdown and other spurious events that might interrupt the erase process (a reset, for example) should be considered when design
ing the Flash memory management software. To design robust Flash memory management software a thorough understanding of the Flash memory erase process is necessary.
Note:In the case of a CPU reset, ongoing sector erase or mass erase operations on the
STM32F40x/STM32F41x embedded Flash are not interrupted.
1.3 Similarity in writing method
One of the similarities between external EEPROM and emulated EEPROM with the
STM32F40x/STM32F41x embedded Flash is the writing method.
●Standalone external EEPROM: once started by the CPU, the writing of a word cannot be interrupted by a CPU reset. Only a supply failure will interrupt the write process, so Read access –Serial: a hundred µs
–Random word: 92 µs
计算机硬件–Page: 22.5 µs per byte Parallel: (@168 MHz) the access time by half-word is from 0.68 µs to 251 µs (2)
CPU speed with 1 wait state
Write/Erase cycles    1 million Write cycles 10 kilocycles by sector (large
page). Using multiple on-chip
Flash memory pages is
equivalent to increasing the
number of write cycles. See
Section 3.4: Cycling capability
and page allocation .No limit as long as VBA T is present
1.For more information about the backup SRAM usage, refer to “Battery backup domain” in STM32F40x/41x Reference Manual  (RM0090).
2.For further detail, refer to Chapter 2.5: EEPROM emulation timing .
Table 1.
Differences between external and emulated EEPROM (continued)Feature External EEPROM (for example, M24C64:
I²C serial access EEPROM)
Emulated EEPROM using on-chip Flash memory Emulated EEPROM using on-chip backup SRAM memory (1)